[vsipl++] [patch] CFAR benchmark storage order

[Don McCoy]

Please disregard the previous version(s) of this patch.  The attached 
version has been checked more thoroughly than before.  This time I ran 
all the sets with varying storage orders for the CFAR data cube, then I 
compared results at the points specified by the HPEC Challenge (in terms 
of the number of range gates, RG). 

This retesting resulted in a change for the "by-vector" algorithm for 
about a 5% performance improvement.  See the table below, produced from 
data taken from the Xeon cluster at GTRI.

                   Slice
        RG      2-0-1   0-2-1
Set 1   64      293     210
Set 2   3500    186     147
Set 3   1909    187     145
Set 4   9900    202     150

                   Vector          Hybrid
        RG      0-1-2   1-0-2   0-1-2   1-0-2
Set 1   64      96      97      384     415
Set 2   3500    125     133     693     666
Set 3   1909    123     130     692     650
Set 4   9900    124     132     697     670

Regards,

-- 
Don McCoy
don (at) CodeSourcery 
(888) 776-0262 / (650) 331-3385, x712

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